Company Overview
Our client is an innovative semiconductor company developing next-generation memory, storage controller, and high-speed interface ASIC solutions.
The engineering team covers architecture, RTL design, SoC integration, firmware, verification, and implementation, giving engineers the opportunity to participate in the complete chip development lifecycle and work closely across hardware and system domains.
Job Summary
The Digital IC Designer will be responsible for architecture definition, RTL design, and SoC integration for next-generation memory, storage controller, and high-speed interface products.
This role goes beyond RTL coding. You will participate in early-stage design discussions, architecture definition, system bus and peripheral design, SoC / emulation platform development, and system performance analysis.
The position is well suited for engineers who want to build deeper expertise in Digital IC Design, SoC Architecture, and System-Level Design.
Responsibilities
- Participate in design concept discussions and SoC architecture definition.
- Perform digital architecture design and RTL implementation.
- Develop RTL using Verilog / SystemVerilog.
- Design and integrate system buses, peripherals, and related control logic.
- Participate in SoC top-level and subsystem integration.
- Develop SoC and hardware emulation platforms.
- Analyze SoC system performance and identify architecture or implementation bottlenecks.
- Work closely with Verification, Firmware, System Architecture, and Physical Design teams.
- Support RTL debugging, design optimization, and functional issue resolution.
- Participate in front-end design flow and design-quality checks.
- Support low-power design and analysis when required.
- Develop Python / TCL scripts to improve design and verification efficiency.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- Familiarity with digital logic and Digital IC Design fundamentals.
- Familiarity with RTL design using Verilog or SystemVerilog.
- Understanding of ASIC / SoC front-end design flow.
- Strong analytical and problem-solving skills.
- Ability to work effectively with cross-functional engineering teams.
- Strong interest in SoC architecture, memory / storage controllers, or high-speed interfaces.
- Fresh graduates with a strong academic foundation in Digital IC Design are also welcome.
Preferred Qualifications
- Experience with SystemVerilog and RTL design.
- Familiarity with AMBA protocols such as AXI, AHB, or APB.
- Experience with SoC integration or subsystem design.
- Knowledge of Python programming.
- TCL scripting experience.
- Familiarity with UVM / SystemVerilog verification methodology.
- Experience with FPGA or hardware emulation platforms.
- Knowledge of low-power design and analysis.
- Familiarity with UPF or multiple power-domain designs.
- Experience with Synopsys, Cadence, or other EDA tools.
- Understanding of memory controllers, storage controllers, PCIe, CXL, or other high-speed interfaces.
- Previous ASIC tape-out experience is a plus.
Post Time｜2026/08/25
