Company Overview

Our client is a global technology company providing advanced design, engineering, manufacturing, and platform solutions for data center infrastructure. 

The company develops high-performance compute, storage, networking, and AI infrastructure platforms for hyperscale and enterprise customers. The Taiwan engineering team is expanding its FPGA / CPLD capability to support next-generation server, storage, and switching products. 

Job Summary

The Senior CPLD / FPGA Engineer will be responsible for FPGA / CPLD architecture, RTL design, verification, implementation, and hardware validation for data center server, storage, and networking platforms. 

This is a system-level FPGA role rather than a pure RTL coding position. You will work closely with Hardware, Firmware, Software, and System Architecture teams to define FPGA / CPLD functionality, review schematics and PCB implementation, complete RTL development and timing closure, and bring the design up on real hardware. 

You will also provide technical guidance to junior engineers and participate in complex system debugging throughout the product-development cycle.

Responsibilities

• Define FPGA / CPLD architecture based on server, storage, and networking system requirements. 

• Work closely with System Architects, Hardware Engineers, and Software / Firmware teams to translate product requirements into FPGA / CPLD solutions. 

• Evaluate technical approaches and select appropriate FPGA / CPLD devices and architectures. 

• Develop design specifications, validation plans, and engineering reports. 

• Design and implement RTL using Verilog / SystemVerilog. 

• Perform module-level verification and develop corresponding test cases. 

• Perform pre-synthesis and post-synthesis simulation. 

• Own FPGA / CPLD implementation flow including synthesis, design constraints, floorplanning, timing analysis, and timing closure. 

• Work with Hardware Engineers on FPGA / CPLD-related schematic design and design reviews. 

• Review PCB implementation including FPGA / CPLD pin assignments, power, interfaces, and board-level constraints. 

• Perform FPGA / CPLD board bring-up and on-board validation. 

• Lead hardware debugging and failure analysis during prototype and system validation. 

• Debug high-speed and low-speed interfaces using oscilloscopes, logic analyzers, and other laboratory equipment. 

• Collaborate with cross-functional teams to resolve issues involving Hardware, Firmware, BIOS / BMC, Software, Manufacturing, Reliability, and Validation. 

• Support design improvements based on manufacturing, reliability, and system-test feedback. 

• Provide accurate project estimates and deliver designs according to development milestones. 

• Mentor junior FPGA engineers and provide technical training and design guidance. 

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, Communications Engineering, or a related field. 

• 5+ years of FPGA / CPLD design experience with a Master’s degree, or equivalent senior-level industry experience. 

• Strong experience with Verilog, SystemVerilog, and RTL design. 

• Strong hands-on experience with FPGA / CPLD development tools such as: 

• • Xilinx / AMD Vivado or ISE 

• • Intel / Altera Quartus 

• • Lattice Diamond 

• ModelSim or equivalent simulation tools 

• Experience with Xilinx / AMD, Intel / Altera, or Lattice FPGA / CPLD devices. 

• Strong understanding of FPGA implementation flow including synthesis, constraints, floorplanning, STA, and timing closure. 

• Experience reviewing hardware schematics and PCB designs. 

• Strong board bring-up and hands-on debugging capability. 

• Proficiency with oscilloscopes, multimeters, logic analyzers, and related hardware-debug tools. 

• Strong analytical and problem-solving skills. 

• Good English communication skills and ability to work with global engineering teams. 

• Ability to manage multiple development projects simultaneously. 

Preferred Qualifications

• Experience developing FPGA / CPLD solutions for server, storage, switch, or data center hardware. 

• Strong understanding of high-speed interfaces such as: 

• • PCIe 

• • Ethernet 

• • USB 

• • DDR 

• • LVDS 

• Familiarity with platform-management and low-speed interfaces including: 

• • SPI 

• • eSPI 

• • I2C 

• • UART 

• • LPC 

• • MDIO 

• Experience with UVM, constrained-random verification, assertions, and functional coverage. 

• Familiarity with server platform control logic, power sequencing, reset architecture, or system-management functions. 

• Experience with BMC / BIOS / CPLD interaction is highly preferred. 

• Knowledge of high-speed board design and Signal Integrity fundamentals. 

• Experience supporting EVT / DVT / system validation and mass-production issue resolution. 

• Experience mentoring junior engineers or acting as a technical lead. 

Post Time｜2026/10/02