The company provides wafer and other service for Tier one companies.
- Meet the target of device performance and examine crucial design of core/IO devices with various Vt flavors, SRAM, etc. and layout dependence effect of 40nm/28nm and beyond
- Work closely with designer to optimize speed and standby performance of various tracks standard cells, GPIO, and memory compilers
- Cooperate with process integration to optimize LOD and drive device IOFF;
- Coordinate with model team for various device behaviors for SPICE model.
- With excellent teamwork ability to cooperate with integration, module, test, CAD, model, design and reliability teams
- Device design and optimization to perform multiple Vt flavors of both poly-SiON and HK/MG technologies.
- With Bachelor/ Master/ PhD in Electronics, Electrical, Physics or relatives.
- 12 years + experiences in process integration
- 3 years + integration manager or minimum 3 years 40/28nm
- Attractive Salary Package
- Good opportunity for career progression