SoC Designer

Company Overview

Our client is a technology company focused on complex SoC / ASIC design and system integration, with capabilities spanning architecture planning, RTL design, design integration, synthesis, timing closure, and physical implementation. 

The team is involved in advanced semiconductor and high-performance computing applications, giving engineers opportunities to participate in the complete RTL-to-GDS flow rather than working only on isolated IP blocks. 

Job Summary

The SoC Designer will participate in SoC top-level and subsystem architecture planning, RTL design integration, and end-to-end implementation from logic synthesis through physical implementation. 

This role goes beyond RTL coding and provides exposure to Synthesis, LEC, STA, Timing Sign-off, DFT, and Physical Design, making it suitable for engineers who want to develop into broader SoC integration or architecture roles. 

Responsibilities

• Participate in SoC top-level and subsystem architecture planning.  

• Perform RTL design and integration using Verilog HDL.  

• Integrate CPU, memory, bus, peripheral, and IP blocks into SoC platforms.  

• Perform RTL sign-off and design-quality checks.  

• Execute logic synthesis and design optimization.  

• Perform Logic Equivalence Check (LEC).  

• Conduct Static Timing Analysis (STA) and timing closure.  

• Support timing sign-off and implementation quality review.  

• Work closely with Physical Design teams to drive RTL-to-GDS implementation.  

• Resolve interface, clock, reset, and timing-related integration issues.  

• Collaborate with Verification, DFT, and Physical Design teams through tape-out.  

• Support FPGA implementation or prototyping when required.  

Requirements

• Bachelor’s degree or above in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.  

• Familiarity with Verilog HDL and digital IC design fundamentals.  

• Understanding of ASIC / SoC design flow.  

• Experience or knowledge in RTL design, synthesis, LEC, STA, and timing sign-off.  

• Good understanding of digital logic and timing concepts.  

• Strong problem-solving and debugging skills.  

• Ability to work effectively with Verification, DFT, and Physical Design teams.  

Preferred Qualifications

• Experience with SoC top-level or subsystem integration.  

• Familiarity with AMBA protocols such as AXI, AHB, or APB.  

• Experience with ARM-based SoC platforms.  

• Knowledge of DFT, ATPG, or MBIST.  

• FPGA implementation experience.  

• Familiarity with Synopsys, Cadence, or other EDA tools.  

• Scripting experience with TCL, Python, or Perl.  

• Knowledge of CDC / RDC analysis.  

• Experience with low-power design, UPF, or multiple power domains.  

• Previous ASIC tape-out experience.  

Post Time｜2026/08/25