Company Overview
Our client is a leading semiconductor design company specializing in advanced ASIC development for high-performance computing, AI, and data center applications.
The company focuses on cutting-edge process nodes and complex system-on-chip (SoC) designs, collaborating with global customers to deliver high-performance and power-efficient silicon solutions.
Engineering teams are involved in full-chip development, from architecture definition to tape-out, working closely with front-end, package, and system teams across global locations.
Job Summary
The Physical Design Manager will lead digital back-end implementation for advanced-node ASIC projects, taking ownership from netlist to GDS sign-off.
This role requires strong expertise in full-chip physical design, timing closure, power integrity, and advanced node challenges, along with the ability to lead teams and drive execution across complex, multi-domain designs.
The position is ideal for experienced physical design engineers looking to step into or grow within a leadership role in advanced SoC development.
Responsibilities
- Lead full-chip physical design implementation from netlist to GDS sign-off for advanced-node ASIC projects
- Define and execute floorplanning strategies, including partitioning, power planning, placement optimization, and pin assignment
- Drive place-and-route, clock tree synthesis (CTS), timing closure, and power optimization
- Oversee analysis and closure of timing, IR drop, signal integrity (SI), and physical verification
- Collaborate with front-end design teams on logic, timing, and clock architecture optimization
- Work with package teams on substrate design and SI/PI considerations
- Guide and mentor team members while ensuring project milestones and tape-out schedules are met
- Continuously optimize design flows, methodologies, and tool usage for improved efficiency and quality
Requirements
- Bachelor’s degree or above in Electrical Engineering, Microelectronics, or related fields
- 5+ years of experience in digital back-end physical design
- Proven experience in full-chip tape-out, preferably in advanced nodes (≤7nm)
- Strong expertise in physical design flow including floorplanning, P&R, CTS, timing closure, and physical verification
- Familiarity with multi-voltage, multi-clock domain designs
- Experience with high-speed interface IPs such as DDR, PCIe, SerDes, or HBM PHY
- Proficiency in scripting (TCL, Python, Perl, Shell)
- Strong problem-solving ability and experience handling complex design challenges
- Good communication skills and working-level English
Preferred Background
- Experience in 5nm or below advanced nodes
- Experience leading small teams or acting as technical lead
- Strong understanding of low power design (UPF), reliability, and noise analysis
- Familiarity with EDA tools such as Primetime, Innovus, Fusion Compiler, Calibre, Redhawk, StarRC
Post Time｜2026/03/24
